IP Portfolio

Technology Foresight Portfolio

   Spintronics AI is actively expanding its IP portfolio to address emerging needs in AI, 5G, automotive, and edge computing. Our in-development IPs focus on ultra-low power, high bandwidth, and system-level integration, especially in SerDes, PMICs, data converters, and chiplet interconnects.

   These IPs are currently in various stages of specification, prototyping, and silicon validation, with early access and co-development opportunities available for strategic partners.

High-Speed Interface & SerDes IPs (In Progress)

PCIe SerDes IP

  • 64 GT/s with PAM4 modulation
  • Forward Error Correction (FEC) and advanced equalization (CTLE, DFE)
  • Designed for data center and AI accelerators
  • Compliant with CXL 2.0+ specifications
  • Supports memory coherency and cache interconnect
  • Targeted for chiplet and server-class SoCs
 

HighSpeed SerDes (Long-Reach/Short-Reach)

  • Multi-protocol support (Ethernet, CEI, OIF)
  • Multi-tap DFE, CTLE, and adaptive EQ
  • Optimized for ultra-low BER and low power
 

Advanced Mixed-Signal & Converter IPs

High-Speed Multi-Channel ADC (≥ 1.5 GSPS)

  • SAR-pipeline hybrid design
  • High ENOB, low power
  • Applications: mmWave, imaging, software-defined radio

Sigma-Delta Modulator IP (for Audio & Industrial)

  • 24-bit resolution, up to 1 MSPS
  • Low noise floor, integrated decimation filters
  • Ideal for audio and precision sensors

Dual-Mode DAC (Current/Voltage Mode)

  • 12–16 bit resolution
  • Configurable output range and reference sources
  • Low glitch, fast settling for control loops
 

Power Management IC (PMIC) IPs Under Development

Digital LDO (DLDO) with Adaptive Biasing

  • Fine-grain voltage control for near-threshold digital blocks
  • Digital control loops and fast transient response
  • DVFS-compatible with real-time telemetry

Integrated Voltage Regulator (IVR) IP

  • Switched-capacitor and buck converter topologies
  • On-die power delivery for CPU, GPU, and AI accelerators
  • Programmable efficiency control and EMI-aware layout

Battery Management IP (BMS Analog Front-End)

  • Multi-cell voltage and current monitoring
  • Over-voltage, under-voltage, and thermal protection
  • Automotive-grade design in progress

Smart Power Sequencer, Supervisor IP & Dynamic Power Scaling Controller

  • Multi-rail sequencing with programmable delay/fault flags
  • Integrated brown-out and glitch detection
  • Designed for FPGAs, SoCs, and multi-domain ASICs
  • Works with hardware P-states / DVFS frameworks
  • Real-time adaptive scaling based on performance modes

Ideal for mobile AI and edge inference SoCs

What’s Next?

At Spintronics AI, innovation is a continuous journey. These IPs are being developed with close collaboration from fabrication partners and lead customers.

Early access, customization, and co-development engagements are now open.

Talk to us to collaborate on next-gen silicon.